1. Field of the Invention
The present invention relates to a SONOS non-volatile memory and a method of controlling a SONOS non-volatile memory, and more particularly, to a multi-value technique for increasing the storage capacity per unit cell without a decrease in the area of each unit cell.
2. Description of the Related Art
There has been a SONOS structure developed as one type of non-volatile memory structure. In the SONOS structure, an ONO film (a laminated film of oxide film/nitride film/oxide film) is used as the gate insulating film to be provided immediately below the gate electrode. Charges are locally accumulated in the nitride film (generally, a silicon nitride film) in the vicinity of the source region and the drain region and data storage by two bits per cell can be carried out.
FIGS. 1A through 1C are schematic views of the multi-value cell structure of a SONOS non-volatile memory as disclosed by Boaz Eitan et al., in Electron Device Letters, Vol. 21, No. 11, p543-545 (2000) (“Boaz et al.”). FIG. 1A is a schematic plan view of a cell and its vicinity area. FIG. 1B is a schematic cross-sectional view of the area in the vicinity of the single cell, taken along the line A-A′ of FIG 1A. FIG. 1C is a schematic cross-sectional view of the area in the vicinity of the single cell, taken along the line B-B′ of FIG. 1A.
In FIG. 1A, the region surrounded by the broken line is the region of a single memory cell 10. This single cell 10 is located in a region in which two bit lines 13 (BL1) and 14 (BL2) cross a word line 15 (WL1). The two bit lines 13 and 14 extend in the vertical direction of the drawing, and have electrodes 17 and 18 to which a bias can be applied. The word line 15 extends in the horizontal direction of the drawing. The single cell 10 is a 2-bit multi-value cell, and has two charge accumulation regions 11 and 12. A word line 16 (WL2) is connected to a single cell (not shown) that is located on the lower side of the drawing and is adjacent to the single cell 10.
As shown in FIG. 1B, an ONO film is formed as a gate insulating film 19 on the bit lines 13 and 14. The ONO film is a three-layer structure that includes a lower silicon oxide film 20, a silicon nitride film 21, and an upper silicon oxide film 22 stacked in this order. The word line 15 is formed on the ONO film. Two portions of the silicon nitride film 21 in the vicinity of the bit lines 13 and 14 serve as charge accumulation regions 11 and 12 for holding and releasing charge in accordance with applied bias. The charge accumulation regions 11 and 12 are mirror symmetric to each other. In short, the charge accumulation regions constitute a mirror bit structure. As shown in FIG. 1C, side walls 23 are formed on side faces of the word line 15 and the gate insulating film 19.
FIGS. 2A through 2D illustrate a situation in which charges are held in the SONOS non-volatile memory illustrated in FIGS. 1A through 1C. FIGS. 2A through 2D are schematic cross-sectional views of the SONOS non-volatile memory taken along the line A-A′ of FIG. 1A. As described above, the single cell 10 has the two charge accumulation regions 11 and 12. Accordingly, four different charge holding states (storage states) can be observed through combinations of the state in which charges are accumulated in a charge accumulation region (represented by “0”) and the state in which charges are not accumulated in a charge accumulation region (represented by “1”). More specifically, FIG. 2A shows the state (11) in which charges are not accumulated in either of the charge accumulation regions 11 and 12. FIG. 2B shows the state (01) in which charges are accumulated in the charge accumulation region 11 but are not accumulated in the charge accumulation region 12. FIG. 2C shows the state (10) in which charges are accumulated in the charge accumulation region 12 but are not accumulated in the charge accumulation region 11. FIG. 2D shows the state (00) in which charges are accumulated in both of the charge accumulation regions 11 and 12.
Recently, increasing memory capacity has been one of the critical objectives in the development of non-volatile memories. The SONOS non-volatile memory disclosed by Boaz Eitan et al., has a storage capacity of 2 bits per cell. However, to further increase the memory capacity, it is necessary to reduce the area of each unit cell through miniaturization techniques.
However, when a memory is manufactured in accordance with these miniaturization techniques so as to reduce the cell area, a new technology for avoiding technical problems caused in conjunction with the miniaturizing process is demanded, and an increase in production costs is caused. As a result, a technique for increasing the storage capacity per unit cell without a decrease in unit cell area is required.